1. Technical Field of the Invention
This disclosure relates generally to electronic circuits, and more particularly, to complimentary metal oxide silicon (CMOS) voltage level translation circuits.
2. Description of the Related Art
For purposes of this disclosure, a voltage level translation circuit is defined as a circuit that transforms an input signal having a first amplitude swing range into an output signal having a second amplitude swing range, the first and second amplitude swing ranges being different.
Voltage level translation circuits are typically used when the core of a chip operates at a voltage that is different (usually lower) than that of the input/output buffers. In the case of CMOS logic the logical one signal levels generated by logic connected to the supply with the lower voltage are not sufficient to turn off the gates of P-channel Metal-Oxide-Semiconductor (PMOS) devices whose sources are connected to the supply with the higher voltage. This scenario leads to substantial wasted current dissipation on the supply with the higher voltage.
FIG. 1 is a circuit diagram illustrating a conventional voltage level translation circuit 100. The voltage level translation circuit 100 includes an input signal IN coupled to the gate of a first transistor N1 and to the input of an inverter I1, where the output of the inverter is coupled to the gate of a second transistor N2. The voltage level translation circuit 100 further includes a third transistor P1 and a fourth transistor P2 having cross-coupled gates and drains, wherein the drain of the third transistor P2 is coupled to the source of the first transistor, and the drain of the fourth transistor is coupled to the source of the second transistor. The output of the voltage level translation circuit 100 is coupled to the source of the second transistor N2.
The voltage level translation circuit 100 operates in the following manner. When the input is low, the third transistor P1 is on, the first transistor N1 is off, the fourth transistor P2 is off, and the third transistor P1 holds out low. When the input transitions from low to high, the first transistor N1 turns on immediately, fighting the third transistor P1, the second transistor N2 turns off, and the fourth transistor P2 turns on weakly to pull out high and turn off the third transistor P1.
When the input is high, the third transistor P1 is off, the first transistor N1 is on, the fourth transistor P2 holds out high, and the second transistor N2 is off. When the input goes from high to low the first transistor N1 turns off immediately, the second transistor N2 turns on, fighting the fourth transistor P2, and starts pulling low. The third transistor P1 turns on weakly (because it is pulled down) and turns the fourth transistor P2 off.
Disadvantages of the conventional voltage level translation circuit 100 include, depending upon the exact implementation, a greater duty cycle distortion (DCD) or a longer latency, or both, than what may be desired by a user. This distortion and latency results from the contention (fighting) in the speed path, as was described above.
Embodiments of the invention address these and other disadvantages of the conventional art.